Output buffer with constant switching current

ABSTRACT

The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to integrated circuits and, moreparticularly, to an output buffer for digital signals.

[0003] 2. Description of the Related Art

[0004] As is known, in an integrated circuit, an output buffer fordigital signals is an interface circuit which serves for driving a loadwhich, in most cases, is outside the integrated circuit. Normally, thecircuit is dimensioned on the basis of direct-current operatingspecifications, that is, on the basis of the maximum value of the supplyvoltage and on the maximum value of the current to be supplied to apredetermined resistive load. As a result of this dimensioning, theswitching speed is often much greater than required and this may giverise to serious disadvantages. In particular, as the number of functionswhich can be integrated in a single chip of semiconductor materialincreases, the number of outputs of the integrated device increases. Theoutputs are often grouped in “buses” and have to be switchedsimultaneously by the respective output buffers. In these cases, veryhigh pulsed currents pass through the impedances and the parasiticresistances associated with the electrical connections between theintegrated circuit and the external terminals during switching. Thesecurrent transients require the external supply to deliver, for veryshort periods, currents much greater than those required on average forthe operation of the device, and therefore necessitate the use ofover-dimensioned supply means. This problem is experienced in particularwhen the integrated device forms part of portable apparatus, that is, ofapparatus having limited electrical energy resources. Moreover, thecurrent transients may give rise to spurious internal switching, andhence to losses or alterations of the data associated with the digitalsignal. In mixed integrated circuits, that is, those containing bothdigital portions and analog portions, the current transients mayprejudice the performance of the analog circuits.

[0005] To prevent or at least attenuate the problems explained above,devices must be designed with supply-connection tracks of sufficientlylarge cross-section. A solution of this type is completelyunsatisfactory since it leads to a great wastage of area and does notsolve the problem of excessive demands on the supply.

[0006] A known output buffer designed to address the problems explainedabove is shown in FIG. 1. In this example, the buffer is constituted byfour pairs of complementary MOS transistors connected so as to operatein phase opposition, in pairs (M1n-M4n; M1p-M4p), but it could beconstituted by a much larger number of such pairs. The pairs oftransistors are connected between two supply terminals, indicated by theearth symbol and +VDD, and have, as a common terminal, the drainelectrodes of the transistors which are connected to an output terminalOUT. The gate electrodes of the first pair M1p, M1n are connectedtogether to the input terminal IN of the buffer and the gate electrodesof the subsequent pairs are connected together to the gate electrodes ofthe respective preceding pairs by means of delay circuits which, in thisexample, have equal delay times Δt. The transistors are of a size suchthat each pair can supply one quarter of the output current to the load,not shown. As a result of the delays, a transition in the level of asignal applied to the input IN gives rise to a much slower transition inthe output signal than in the input signal, reducing any current peaks.However, this circuit operates satisfactorily only if it is constitutedby a large number of pairs of transistors. This involves the wastage ofa large area of the integrated circuit so that this solution is not inpractice very much favoured by designers.

[0007] Another known buffer is shown schematically in FIG. 2. It isformed by a single pair of complementary MOS transistors Mp and Mncontrolled by respective driver stages DRp and DRn. The stages DRp andDRn operate in a manner such as to switch the respective transistors offrapidly and to switch them on slowly by the generation of aconstant-current front long enough to cause the output OUT to switchgradually. However, this known buffer is rather complex and, in the samemanner as the other known buffer described briefly above, supplies acurrent which varies in dependence on the load.

BRIEF SUMMARY OF THE INVENTION

[0008] Aspects of the present invention involve an output buffer fordigital signals in which the switching current, that is, the currentdelivered or absorbed during the transitions of the digital signal, isindependent of the load. Aspects also include an output buffer fordigital signals which is simple and reliable and occupies a small area.

[0009] Further to these and other aspects, an output buffer for digitalsignals has an output stage including a first output MOS transistor of afirst type and a second MOS transistor of a second type with respectivesource electrodes connected to a first supply terminal and to a secondsupply terminal, respectively, drain electrodes connected together to anoutput terminal (OUT) of the buffer, and gate electrodes connected to aninput terminal of the buffer by means of a first driver stage and asecond driver stage, respectively.

[0010] The first driver stage includes a first circuit branch comprisingfirst current-generator means connected between the gate electrode ofthe first output transistor and the second supply terminal and a firstcontrolled electronic switch connected between the gate electrode of thefirst output transistor and the first supply terminal and having acontrol electrode connected to the input terminal of the buffer. Thefirst driver further includes a second circuit branch comprising a firstMOS transistor of the first type connected as a diode in series with asecond controlled electronic switch between the gate electrode of thefirst output transistor and the first supply terminal, the secondelectronic switch having a control terminal connected to the outputterminal of the buffer.

[0011] A second driver stage includes a third circuit branch comprisingsecond current-generator means connected between the gate electrode ofthe second output transistor and the first supply terminal and a thirdcontrolled electronic switch connected between the gate electrode of thesecond output transistor and the second supply terminal (earth) andhaving a control electrode connected to the input terminal of thebuffer. The second driver stage further includes a fourth circuit branchcomprising a second MOS transistor of the second type connected as adiode in series with a fourth controlled electronic switch between thegate electrode of the second output transistor and the second supplyterminal, the fourth electronic switch having a control terminalconnected to the output terminal of the buffer.

[0012] Other features and advantages of the invention will becomeapparent from the following detailed description, taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0013] The invention will be understood further from the followingdetailed description of two embodiments thereof, given by way ofnon-limiting example, with reference to the appended drawings, in which:

[0014]FIGS. 1 and 2 show the circuits of two known buffers,

[0015]FIG. 3 shows the circuit of a buffer according to a firstembodiment of the invention,

[0016]FIG. 4 shows some wave-forms which illustrate the operation of thecircuit of FIG. 3,

[0017]FIG. 5 shows a second embodiment of the invention, and

[0018]FIG. 6 shows the circuit of a possible practical implementation ofthe embodiment of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The circuit shown in FIG. 3 comprises an output stage 10 withcomplementary MOSFET transistors, more precisely, a p-channel transistorMPOUT and an n-channel transistor MNOUT, connected so as to operate inphase opposition between a first supply terminal +VDD and a secondsupply terminal, indicated by the earth symbol. The node common to thetwo transistors, that is, the connection node between their two drainelectrodes, is the output terminal OUT of the buffer and is connected,by means of a respective pin of the integrated circuit, to an externalload 13, typically a substantially capacitive load.

[0020] The circuit comprises two stages 14 and 15 for driving thetransistors of the output stage 10. The driver stage 14 is constitutedby two circuit branches: a first circuit branch comprises an n-channelMOS transistor MN4 and a p-channel MOS transistor MP1. The transistorMN4 which, as will be explained below, has the function of generatingcurrent, has its source electrode connected to earth, its drainelectrode connected to the gate electrode of the output transistorMPOUT, and its gate electrode connected to the input terminal IN of thebuffer. The transistor MP1, which has the function of a controlledelectronic switch, has its gate electrode connected to the inputterminal IN of the buffer. The second circuit branch of the driver stage14 comprises a p-channel MOS transistor MP3 connected in the so-calleddiode arrangement, that is, with its gate and drain connected to oneanother, in series with a p-channel MOS transistor MP2 having thefunction of a controlled electronic switch. The common electrodes of thetransistor MP3 are connected to the gate electrode of the outputtransistor MPOUT and the gate electrode of the transistor MP2 isconnected to the output terminal OUT of the buffer.

[0021] The driver stage 15, as can be seen from FIG. 3, is constitutedby a third branch (MP4, MN1) and by a fourth branch (MN3, MN2) havingstructures corresponding to those of the first and second branches ofthe driver stage 14.

[0022] Before the operation of the buffer of FIG. 3 is examined, it isappropriate to make some remarks relating to the nature and thedimensions of the transistors which form parts thereof. The dimensionsof the output transistors MPOUT and MNOUT are determined by the samecriteria as are used for the buffer of the prior art, that is, on thebasis of the maximum value of the supply voltage and on the maximumvalue of the current to be supplied to a resistive load duringdirect-current operation. The transistor MP2 must operate substantiallyas a switch and must therefore have as low as possible an impedance whenit is made conductive. The transistor MP3 must conduct a current whichis a predetermined fraction of the current of the output transistorMPOUT and will therefore have dimensions correspondingly correlated withthose of the transistor MPOUT (typically, it will have the same channellength and a width which is a fraction of the width of MPOUT). Thetransistor MN4 is intended to operate in saturation conditions, that is,with a large impedance, and must be able to supply the necessary currentto MP3. The transistor MP1 is intended to operate as a switch forrapidly interrupting conduction of the output transistor MPOUT whenrequired and is therefore dimensioned accordingly. Wholly similarremarks may be made with regard to the dimensions of the transistors ofthe driver stage 15 of the output transistor MNOUT.

[0023] The operation of the buffer during a switch from 0 to 1 of adigital signal applied to the input terminal IN will now be consideredwith reference to FIG. 4. It can easily be seen that, in the absence ofa signal, with the input IN at level 0, that is, at the earth potential,the output OUT is also at 0, that is, MNOUT is conductive (on) and MPOUTis nonconductive (off). When the signal is applied to the input IN,immediately after the leading edge from 0 to 1, MP4 becomesnon-conductive (off) and MN1 becomes conductive (ON). The outputtransistor MNOUT switches off because its gate electrode DN goes to 0.At the same time, in the driver stage 14, MP1 switches off and MN4switches on. Since the output OUT is at 0, MP2 is on so that a currentflows through MP2, MP3 and MN4, connected in series. At the gateelectrode DP of the output transistor MPOUT, there will be a voltageVDD-VDS (MP2)-VTH (MP3)-VOD (MP3), that is, the supply voltage VDD,minus the voltage drop in MP2 in saturation conditions, minus thethreshold voltage of MP3, minus the voltage beyond the threshold(overdrive) due to the current imposed by MN4 in MP3. By way ofindication, the voltage at the node DP will be below the supply voltageVDD by a value of between 0.7 and 1.5V, according to the relativedimensions of the various transistors. In these conditions, the outputtransistor MPOUT, which was initially off, starts to conduct a currentsubstantially proportional to that which passes through the transistorMP3 and to charge the capacitance of the load 13. The coefficient ofproportionality is determined by the scale factor, that is, by thedimensional ratio between MPOUT and MP3. This situation is maintainedthroughout the time for which MP2 remains on. When the voltage at theoutput terminal OUT reaches a value equal to VDD minus the threshold ofMP2, minus the overdrive of MP2 (very small if MP2 is of a suitablesize), MP2 switches off, interrupting the flow of current through MP3and MN4. Since MN4 is still on because the input IN is at high level(VDD), the node DP goes to 0, MPOUT is switched on and the output OUTgoes to VDD. The rise in the voltage at the output OUT to VDD takesplace with a constant rate of change (slew rate) for the greater portionof its swing, that is, the portion determined substantially solely bythe current reflected by MP3 on MPOUT. The small residual swing iscontrolled by the zeroing rate of the node DP, that is, by thecapacitance associated therewith (substantially the gate capacitance ofMPOUT) and does not lead to a substantial increase in the current of theoutput transistor MPOUT which operates in the linear zone in theseconditions.

[0024] When the input IN goes from 1 to 0, the output OUT switches from1 to 0 in a manner precisely mirroring that described above.

[0025] As is clear from the foregoing, in the buffer according to thisdepicted embodiment of the invention, the current delivered to the load13 or absorbed thereby during the transitions of the signal issubstantially independent of the load and is determined basically by thedimensions of the components of the driver stages. It should also benoted that, in contrast with the known buffer shown in FIG. 2, in whichthe slow voltage variation front at each of the gate electrodes of theoutput transistors is inactive until the threshold of the respectiveoutput transistor is exceeded, with a consequent delay of the outputsignal, the response of the buffer according to this depicted embodimentof the invention is very rapid since the charging of the gatecapacitances of the output transistors takes place by means of theseries connection of a transistor connected as a diode (MP3 or MN3) andof a transistor with the function of a switch (MP2 or MN2), both ofwhich have low resistance. Finally, the area required to produce thebuffer according to this depicted embodiment of the invention is verysmall, by virtue of the low number of components.

[0026] According to the embodiment shown in FIG. 5, the transistors MN4and MP4 of FIG. 3, which have the function of current generators, arereplaced by constant-current generators IGEN1 and IGEN2 in series withrespective transistors MN5 and MP5 having the function of switchescontrolled by the input signal. The constant-current generators IGEN1and IGEN2 may be formed with the use of n-channel and p-channeltransistors, respectively, connected as current mirrors to a biasingcircuit. A biasing circuit may be provided in the integrated circuit forother purposes so that, in this case, further components are notnecessary to complete the buffer, or the biasing circuit may be formedappropriately.

[0027]FIG. 6 shows a possible embodiment of the biasing circuit. Thetransistors MIGEN1 and MIGEN2 which perform the functions of thegenerators IGEN1 and IGEN2 of FIG. 5 are connected as current mirrors totwo transistors, MN6 and MP6, respectively, which are connected asdiodes in series with a resistor R, between the supply terminals VDD andearth. The current reflected is determined substantially solely by thesupply voltage and by the resistance R and, to a large extent, isinsensitive to variations of the process parameters and of the operatingtemperature of the circuit. It should also be noted that the transistorsMIGEN1 and MIGEN2 are conductive only during the transitions in thelevel of the input signal, by virtue of the action of the seriestransistors MN4 and MP5, respectively, so that their contribution to theconsumption of electrical energy is very limited.

[0028] Although only two embodiments of the invention have beendescribed and illustrated, clearly many variations and modifications arepossible within the scope of the same inventive concept. For example,the buffer may be used to control an internal load of the integratedcircuit which contains the buffer, rather than for controlling anexternal load as in the embodiments described. Accordingly, theinvention is not limited except as by the appended claims.

1. An output buffer for digital signals, the output buffer comprising:first and second supply terminals; input and output terminals; an outputstage including: a MOS first output transistor of a first type with asource electrode connected to the first supply terminal, a drainelectrode connected to the output terminal, and a gate electrodeconnected through the first driver stage to the input terminal; and aMOS second output transistor of a second type with a source electrodeconnected to the second supply terminal a drain electrode connected tothe output terminal, and a gate electrode connected to the inputterminal; a first driver stage connecting the gate electrode of thefirst output transistor to the input terminal and including: a firstcircuit branch having: a first current-generator means connected betweenthe gate electrode of the first output transistor and the second supplyterminal; and a first controlled electronic switch connected between thegate electrode of the first output transistor and the first supplyterminal, the first controlled electronic switch having a controlelectrode connected to the input terminal of the buffer; and a secondcircuit branch having: a first MOS transistor of the first typeconnected as a diode in series with a second controlled electronicswitch between the gate electrode of the first output transistor and thefirst supply terminal, the second electronic switch having a controlterminal connected to the output terminal of the buffer; and a seconddriver stage connecting the gate electrode of the second outputtransistor to the input terminal and including: a third circuit branchhaving: a second current-generator means connected between the gateelectrode of the second output transistor and the first supply terminal;and a third controlled electronic switch connected between the gateelectrode of the second output transistor and the second supplyterminal, the third controlled electronic switch having a controlelectrode connected to the input terminal of the buffer; and a fourthcircuit branch having: a second MOS transistor of the second typeconnected as a diode in series with a fourth controlled electronicswitch between the gate electrode of the second output transistor andthe second supply terminal, the fourth electronic switch having acontrol terminal connected to the output terminal of the buffer.
 2. Theoutput buffer according to claim 1 in which the first current-generatormeans comprises a third MOS transistor of the second type having itsgate terminal connected to the input terminal of the buffer and thesecond current-generator means comprises a fourth MOS transistor of thefirst type having its gate terminal connected to the input terminal ofthe buffer.
 3. The output buffer according to claim 1 in which the firstcurrent-generator means comprises a first current generator in serieswith a fifth controlled electronic switch having a control terminalconnected to the input terminal of the buffer and the secondcurrent-generator means comprises a second current generator in serieswith a sixth controlled electronic switch having a control terminalconnected to the input terminal of the buffer.
 4. The output bufferaccording to claim 3 wherein the first and second current generators areconstant current generators.
 5. The output buffer according to claim 3wherein each of the first and second current generators includes atransistor connected as current mirrors to another transistor.
 6. Theoutput buffer according to claim 1 wherein the output buffer is on anintegrated circuit and a load external to the integrated circuit isconnected to the output terminal.
 7. The output buffer according toclaim 1 wherein the output buffer is on an integrated circuit and a loadon the integrated circuit is connected to the output terminal.
 8. Theoutput buffer according to claim 1 wherein the first type is P and thesecond type is N.
 9. The output buffer according to claim 1 wherein thefirst supply terminal is VDD and the second supply terminal is earth.10. A method for buffering an input signal being input into a bufferinput and being switched from a first input value to a second inputvalue to switch an output signal on a buffer output connected to acapacitive load from an first output value associated with the firstinput value to a second output value associated with the second outputvalue, the method comprising: prior to the input digital signal beingswitched from the first value to the second value, causing a firstelectronic switch to be conducting by supplying the first output signalto a control terminal of the first electronic switch; subsequent to theinput digital signal being switched from the first value to the secondvalue, causing a first electrical current having an amount to flow bycausing a second electronic switch to be conducting by supplying theinput digital signal to a control terminal of the second electronicswitch, the second electronic switch connected in series with the firstelectronic switch with a diode device connected between the firstelectronic switch and the second electronic switch, the first electricalcurrent flowing through the second electronic switch, the diode deviceand the first electronic switch; prior to the input digital signal beingswitched from the first value to the second value, supplying a voltagehaving a first value to a control terminal of a third electronic switchhaving a output terminal connected to the buffer output, the firstvoltage causing the third electronic switch to be non-conducting; andsubsequent to the input digital signal being switched from the firstvalue to the second value, changing the voltage being supplied to thecontrol terminal of the third electronic switch from the first value bya voltage difference substantially proportional to the amount of thefirst electrical current to cause a second electrical current to flowthrough the third electronic switch to change the voltage level on thecapacitive load from the first output value toward the second outputvalue.
 11. The method of claim 10 wherein the diode device is atransistor.
 12. The method of claim 10 wherein the first, second, andthird electronic switches are transistors.
 13. The method of claim 10wherein the second input value is greater than the first input value.14. A system for buffering an input signal being switched from a firstinput value to a second input value to switch an output signal from anfirst output value associated with the first input value to a secondoutput value associated with the second output value, the systemcomprising: means for causing a first means for electronic switching tobe conducting by supplying the first output signal to a means forcontrol of the first means for electronic switching prior to the inputdigital signal being switched from the first value to the second value;means for causing a first electrical current having an amount to flow bycausing a second means for electronic switching to be conducting bysupplying the input digital signal to a means for control of the secondmeans for electronic switching, the second means for electronicswitching connected in series with the first means for electronicswitching with a means for diode control connected between the firstmeans for electronic switching and the second electronic means forswitching, the first electrical current flowing through the second meansfor electronic switching, the means for diode control and the firstmeans for electronic switching subsequent to the input digital signalbeing switched from the first value to the second value; means forsupplying a voltage having a first value to a means for control of athird means for electronic switching having a means for output connectedto a means for output of the system, the first voltage causing the thirdmeans for electronic switching to be non-conducting prior to the inputdigital signal being switched from the first value to the second value;and means for changing the voltage being supplied to the means forcontrol of the third means for electronic switching from the first valueby a voltage difference substantially proportional to the amount of thefirst electrical current to cause a second electrical current to flowthrough the third means for electronic switching to change the voltagelevel on a means for capacitive load connected to the means for outputfrom the first output value toward the second output value, subsequentto the input digital signal being switched from the first value to thesecond value.
 15. The system of claim 14 wherein the second input valueis greater than the first input value.
 16. A buffer for digital signals,comprising: first and second supply terminals: input and outputterminals; an output stage including first and second output transistorsconnected between the first and second supply terminals, the first andsecond output transistors being connected to each other at the outputterminal; a first driver stage including: a first inverter connectedbetween the input terminal and a control terminal of the first outputtransistor; and a pull-up transistor connected between the first supplyterminal and the control terminal of the first output transistor, andhaving a control terminal connected to the output terminal; and a seconddriver stage including: a second inverter connected between the inputterminal and a control terminal of the second output transistor; and apull-down transistor connected between the second supply terminal andthe control terminal of the second output transistor, and having acontrol terminal connected to the output terminal.
 17. The buffer ofclaim 16 wherein the first inverter includes: first and second invertertransistors connected to each other at an output terminal of the firstinverter and having respective control terminals coupled to each otherand to the input terminal; and a first current generator connectedbetween the second inverter transistor and the second supply terminal.18. The buffer of claim 17 wherein the first current generator includes:a first mirror transistor connected between the second invertertransistor and the second supply terminal; and a second mirrortransistor connected between the first and second supply terminals andhaving a control terminal coupled to a control terminal of the firstmirror transistor.
 19. The buffer of claim 18 wherein the secondinverter includes: third and fourth inverter transistors connected toeach other at an output terminal of the second inverter and havingrespective control terminals coupled to each other and to the inputterminal; and a second current generator connected between the thirdinverter transistor and the first supply terminal, wherein the secondcurrent generator includes: a third mirror transistor connected betweenthe third inverter transistor and the first supply terminal; and afourth mirror transistor connected between the first supply terminal andthe second mirror transistor and having a control terminal coupled to acontrol terminal of the third mirror transistor.
 20. The buffer of claim16 wherein the first driver stage includes a diode-connected transistorconnected between the pull-up transistor and the control terminal of thefirst output transistor.